Semiconductor device

ABSTRACT

A semiconductor device includes a semiconductor substrate, a silicon carbide semiconductor layer disposed on the semiconductor substrate, and a termination region disposed in the silicon carbide semiconductor layer. The termination region has a guard ring region and an FLR region which is disposed to surround the guard ring region while being separated from the guard ring region, the FLR region including a plurality of rings. The termination region includes a sector section, and in the sector section, an inner circumference and an outer circumference of at least one of the plurality of rings and an inner circumference and an outer circumference of the guard ring region have a same first center of curvature, the first center of curvature being positioned inside the inner circumference of the guard ring region, and a radius of curvature of the inner circumference of the guard ring region is 50 μm or less.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

Silicon carbide (SiC) is a semiconductor material having a greaterbandgap and a greater degree of hardness, compared with silicon (Si).SiC is applied to semiconductor devices such as switching devices andrectifying devices. A semiconductor device made of SiC canadvantageously reduce a power loss, for example, compared with asemiconductor device made of Si.

Typical semiconductor devices made of SiC includemetal-insulator-semiconductor field-effect transistors (MISFETs) andSchottky-barrier diodes (SBDs). A metal-oxide-semiconductor field-effecttransistor (MOSFET) is one kind of MISFETs. A junction-barrier Schottkydiode (JBS) is one kind of SBDs.

A semiconductor device made of SiC (hereinafter referred to as “SiCsemiconductor device”) includes a semiconductor substrate and asemiconductor layer. The semiconductor layer is made of SiC, and isdisposed on a main surface of the semiconductor substrate. Above thesemiconductor layer, an electrode is disposed as a front face electrodefor electrical external connecting. At (or around) a terminal of the SiCsemiconductor device, a termination structure is provided on thesemiconductor layer that alleviates an electric field (see PTL 1).

CITATION LIST Patent Literature

PTL 1: Unexamined Japanese Patent Publication No. 2008-300506

SUMMARY

A highly reliable semiconductor device has been demanded for use in ahigh-voltage and large electric current environment.

However, in the conventional SiC semiconductor device disclosed in PTL1, corners of an effective region through which a large electric currentcan flow have small curvature in a plan view for use in a high-voltageenvironment. Therefore, the area of the effective region is reduced,which may raise a possibility of failing to ensure a sufficient amountof electric current.

One aspect of the present disclosure provides a semiconductor device foruse in a high-voltage and large electric current environment.

In order to address the foregoing problem, one aspect of the presentdisclosure includes a semiconductor device described below.Specifically, this semiconductor device includes a semiconductorsubstrate of a first conductivity type, a silicon carbide semiconductorlayer of a first conductivity type, a termination region of a secondconductivity type, a first electrode, and a second electrode. Thesemiconductor substrate of the first conductivity type has a mainsurface and a back surface. The silicon carbide semiconductor layer ofthe first conductivity type is disposed on the main surface of thesemiconductor substrate. The termination region of the secondconductivity type is disposed in the silicon carbide semiconductorlayer. The first electrode is disposed on the silicon carbidesemiconductor layer and forms a Schottky contact with the siliconcarbide semiconductor layer. The second electrode is disposed on theback surface of the semiconductor substrate and forms an ohmic contactwith the semiconductor substrate. The termination region is disposed tosurround a part of a surface of the silicon carbide semiconductor layeras viewed in a normal direction of the main surface of the semiconductorsubstrate. The termination region also has a guard ring region of asecond conductivity type abutting the surface of the silicon carbidesemiconductor layer, and a field limiting ring (FLR) region which isdisposed to surround the guard ring region while being separated fromthe guard ring region, the FLR region including a plurality of rings ofa second conductivity type. The first electrode has a face abutting thesilicon carbide semiconductor layer. The first electrode also abuts theguard ring region at an edge of the face abutting the silicon carbidesemiconductor layer. The termination region has a sector section asviewed in the normal direction of the surface of the silicon carbidesemiconductor layer. In this sector section, an inner circumference andan outer circumference of at least one of the plurality of rings and aninner circumference and an outer circumference of the guard ring regionhave a same first center of curvature. The first center of curvature ispositioned inside the inner circumference of the guard ring region, anda radius of curvature of the inner circumference of the guard ringregion is 50 μm or less.

The aspects of the present disclosure described above may beimplemented, either comprehensively or specifically, by a system, aprocedure, an integrated circuit, a computer program, or a storagemedium. Alternatively, they may be implemented by any desiredcombinations of a system, an apparatus, a procedure, an integratedcircuit, a computer program, and a storage medium.

According to one aspect of the present disclosure, a semiconductordevice for use in a high-voltage and large electric current environmentcan be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a view illustrating a cross section of a semiconductor deviceaccording to an exemplary embodiment of the present disclosure;

FIG. 1B is a plan view illustrating a termination region formed on adrift layer of the semiconductor device according to the exemplaryembodiment of the present disclosure;

FIG. 2 is a plan view illustrating another example of the terminationregion formed on the drift layer of the semiconductor device accordingto the exemplary embodiment of the present disclosure;

FIG. 3 is a diagram illustrating dependence of a breakdown voltage on aradius of curvature in the semiconductor device according to theexemplary embodiment of the present disclosure;

FIG. 4 is a diagram illustrating reverse leakage current-voltagecharacteristics of the semiconductor device according to the exemplaryembodiment of the present disclosure;

FIG. 5 is a schematic sectional view illustrating a method for formingthe semiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 6 is a schematic sectional view illustrating the method for formingthe semiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 7 is a schematic sectional view illustrating the method for formingthe semiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 8 is a schematic sectional view illustrating the method for formingthe semiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 9 is a schematic sectional view illustrating the method for formingthe semiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 10 is a schematic sectional view illustrating the method forforming the semiconductor device according to the exemplary embodimentof the present disclosure;

FIG. 11 is a schematic sectional view illustrating the method forforming the semiconductor device according to the exemplary embodimentof the present disclosure;

FIG. 12 is a schematic sectional view illustrating the method forforming the semiconductor device according to the exemplary embodimentof the present disclosure;

FIG. 13 is a schematic sectional view illustrating the method forforming the semiconductor device according to the exemplary embodimentof the present disclosure;

FIG. 14A is a view illustrating a cross section of a semiconductordevice according to an exemplary embodiment of the present disclosure;

FIG. 14B is a plan view illustrating a termination region and a barrierregion formed on a drift layer of the semiconductor device according tothe exemplary embodiment of the present disclosure;

FIG. 15A is a view illustrating a cross section of a semiconductordevice according to an exemplary embodiment of the present disclosure;

FIG. 15B is a plan view illustrating a termination region and a barrierregion formed on a drift layer of the semiconductor device according tothe exemplary embodiment of the present disclosure;

FIG. 16A is a view illustrating a cross section of a semiconductordevice according to an exemplary embodiment of the present disclosure;

FIG. 16B is a plan view illustrating a termination region and a barrierregion formed on a drift layer of the semiconductor device according tothe exemplary embodiment of the present disclosure;

FIG. 17A is a view illustrating a cross section of a modification of thesemiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 17B is a plan view illustrating a termination region and atermination implantation region formed on a drift layer of themodification of the semiconductor device according to the exemplaryembodiment of the present disclosure;

FIG. 17C is a view illustrating a cross section of a modification of thesemiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 17D is a plan view illustrating a termination region and atermination implantation region formed on a drift layer of themodification of the semiconductor device according to the exemplaryembodiment of the present disclosure;

FIG. 18 is a view illustrating a cross section of a modification of thesemiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 19 is a view illustrating a cross section of a modification of thesemiconductor device according to the exemplary embodiment of thepresent disclosure;

FIG. 20 is a view illustrating a cross section of a modification of thesemiconductor device according to the exemplary embodiment of thepresent disclosure; and

FIG. 21 is a plan view illustrating a modification of the terminationregion formed on the drift layer of the semiconductor device accordingto the exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

Outline of one aspect of the present disclosure is as follows.

A semiconductor device according to one aspect of the present disclosureincludes a semiconductor substrate of a first conductivity type, asilicon carbide semiconductor layer of a first conductivity type, atermination region of a second conductivity type, a first electrode, anda second electrode. The semiconductor substrate of the firstconductivity type has a main surface and a back surface. The siliconcarbide semiconductor layer of the first conductivity type is disposedon the main surface of the semiconductor substrate. The terminationregion of the second conductivity type is disposed in the siliconcarbide semiconductor layer. The first electrode is disposed on thesilicon carbide semiconductor layer and forms a Schottky contact withthe silicon carbide semiconductor layer. The second electrode isdisposed on the back surface of the semiconductor substrate and forms anohmic contact with the semiconductor substrate. The termination regionis disposed to surround a part of a surface of the silicon carbidesemiconductor layer as viewed in a normal direction of the main surfaceof the semiconductor substrate. The termination region also has a guardring region of a second conductivity type abutting the surface of thesilicon carbide semiconductor layer, and a field limiting ring (FLR)region which is disposed to surround the guard ring region while beingseparated from the guard ring region, the FLR region including aplurality of rings of a second conductivity type. The first electrodehas a face abutting the silicon carbide semiconductor layer. The firstelectrode also abuts the guard ring region at an edge of the faceabutting the silicon carbide semiconductor layer. The termination regionhas a sector section as viewed in the normal direction of the surface ofthe silicon carbide semiconductor layer. In this sector section, aninner circumference and an outer circumference of at least one of theplurality of rings and an inner circumference and an outer circumferenceof the guard ring region have a same first center of curvature. Thefirst center of curvature is positioned inside the inner circumferenceof the guard ring region, and a radius of curvature of the innercircumference of the guard ring region is 50 μm or less.

The radius of curvature of the inner circumference of the guard ringregion may be 10 μm or more, for example.

The radius of curvature of the inner circumference of the guard ringregion may be 10 μm or less, for example.

The inner circumference of the guard ring region may have a right-angledcorner, for example.

The termination region may further include at least two straight partswhose inner periphery and outer periphery are formed by a straight line,for example, and the sector section may be disposed to connect ends ofthe at least two straight parts, for example.

A semiconductor device according to one aspect of the present disclosureincludes a semiconductor substrate of a first conductivity type, asilicon carbide semiconductor layer of a first conductivity type, atermination region of a second conductivity type, a first electrode, anda second electrode. The semiconductor substrate of the firstconductivity type has a main surface and a back surface. The siliconcarbide semiconductor layer of the first conductivity type is disposedon the main surface of the semiconductor substrate. The terminationregion of the second conductivity type is disposed in the siliconcarbide semiconductor layer. The first electrode is disposed on thesilicon carbide semiconductor layer and forms a Schottky contact withthe silicon carbide semiconductor layer. The second electrode isdisposed on the back surface of the semiconductor substrate and forms anohmic contact with the semiconductor substrate. The termination regionis disposed to surround a part of a surface of the silicon carbidesemiconductor layer as viewed in a normal direction of the main surfaceof the semiconductor substrate. The termination region has a guard ringregion of a second conductivity type abutting the surface of the siliconcarbide semiconductor layer, and a field limiting ring (FLR) regionwhich is disposed to surround the guard ring region while beingseparated from the guard ring region, the FLR region including aplurality of rings of a second conductivity type. The first electrodehas a face abutting the silicon carbide semiconductor layer. The firstelectrode also abuts the guard ring region at an edge of the faceabutting the silicon carbide semiconductor layer. The termination regionhas a sector section as viewed in the normal direction of the surface ofthe silicon carbide semiconductor layer. In this sector section, aninner circumference and an outer circumference of at least one of theplurality of rings and an outer circumference of the guard ring regionhave a same first center of curvature. The first center of curvature ispositioned on the inner circumference of the guard ring region or withinthe guard ring region.

When a width of the guard ring region is defined as W (μm), the radiusof curvature of the outer circumference of the guard ring region may be50+W (μm) or less, for example.

The inner circumference of the guard ring region may have a secondcenter of curvature different from the first center of curvature, forexample. In this case, the second center of curvature may be positionedinside the inner circumference of the guard ring region as viewed in thenormal direction of the surface of the silicon carbide semiconductorlayer, for example. The radius of curvature of the inner circumferenceof the guard ring region may be 10 μm or less, for example.

The termination region may further have at least two straight partswhose inner periphery and outer periphery are formed by a straight line,for example. The sector section may be disposed to connect ends of theat least two straight parts, for example.

An exemplary embodiment of the present disclosure will now be describedin detail. However, descriptions in more detail than necessary may beomitted. For example, the detailed description of well-known matters andrepeated description of substantially the same configuration may beomitted. This is to avoid the following description from beingunnecessarily redundant, and to facilitate understanding by thoseskilled in the art. The inventor of the present disclosure provides theappended drawings and the following description in order to allow thoseskilled in the art to fully understand the present disclosure, and doesnot intend to limit the subject matter described in the appended claimsby the appended drawings and the following description. In the followingdescription, components having identical or similar functions aredenoted by the same reference numerals or symbols.

Exemplary Embodiment

A semiconductor device according to an exemplary embodiment of thepresent disclosure will now be described herein with reference to theaccompanying drawings. This exemplary embodiment describes, but notlimited to, an example where a first conductivity type is n-type, and asecond conductivity type is p-type. In the exemplary embodiment of thepresent disclosure, the first conductivity type may be p-type, and thesecond conductivity type may be n-type.

(Structure of Semiconductor Device)

Semiconductor device 100 according to the present exemplary embodimentwill be described with reference to FIGS. 1A to 13.

FIGS. 1A and 1B respectively are a sectional view and a plan viewschematically illustrating semiconductor device 100 according to theexemplary embodiment. Semiconductor device 100 includes semiconductorsubstrate 101 of a first conductivity type and drift layer 102. Driftlayer 102 is a silicon carbide semiconductor layer of a firstconductivity type disposed on a main surface of semiconductor substrate101. While buffer layer 102B is provided between drift layer 102 andsemiconductor substrate 101 in FIG. 1A, buffer layer 102B may not beprovided. Termination region 150 of a second conductivity type isdisposed in drift layer 102. Termination region 150 of the secondconductivity type includes guard ring region 151 and field limiting ring(FLR) region 152 which surrounds guard ring region 151 and includes aplurality of rings.

First electrode 159 is disposed on drift layer 102. First electrode 159forms a Schottky contact with drift layer 102. First electrode 159 abutsguard ring region 151 at an edge of a face abutting drift layer 102which is a silicon carbide semiconductor layer. A metal materialabutting guard ring region 151 may be only first electrode 159. Guardring region 151 may have a non-ohmic contact with first electrode 159.Front face electrode 112 is disposed on a surface of first electrode159.

Insulating film 111 is disposed on a part of surface 102S of drift layer102 so as to cover a part of termination region 150. A part of firstelectrode 159 may cover insulating film 111 from above. Passivation film114 is disposed to cover a part of insulating film 111 from above.Passivation film 114 may cover a part of front face electrode 112.

Second electrode 110 is disposed on a back surface which is on theopposite side of semiconductor substrate 101 from the main surface.Second electrode 110 forms an ohmic contact with semiconductor substrate101. Back face electrode 113 is disposed on a lower face of secondelectrode 110, i.e., a face opposite to a face abutting semiconductorsubstrate 101.

As illustrated in FIG. 1A, termination region 150 may have guard ringregion 151 of a second conductivity type abutting a part of firstelectrode 159 and FLR region 152. FLR region 152 is a floating region ofa second conductivity type disposed to surround guard ring region 151and including a plurality of rings. FLR region 152 is disposed so as notto be in contact with guard ring region 151. Termination region 150 isnot limited to have the configuration described above, as long as it hasat least one region disposed to surround a part of the surface of driftlayer 102. For example, termination region 150 may have ajunction-termination extension (JTE) structure through which aconcentration of impurities that are the second conductivity type variesin the in-plane direction of semiconductor substrate 101.

FIG. 1B is a plan view illustrating surface 102S of drift layer 102 ofsemiconductor device 100. For simplifying the description, components onsurface 102S of drift layer 102 are not illustrated. A region insidetermination region 150 is effective region 102A, and an electric currentflows through effective region 102A on surface 102S of drift layer 102.A region other than effective region 102A on surface 102S of drift layer102 is defined as surrounding region 102E. Surrounding region 102Eincludes guard ring region 151 and FLR region 152. Note that a chip endof semiconductor device 100 is indicated as 100E. In this example,semiconductor device 100 is cut into a square shape. However,semiconductor device 100 may be cut into a rectangular shape or otherpolygonal shapes. Generally, semiconductor device 100 is cut into arectangular shape from a circular semiconductor wafer.

When a negative voltage with respect to second electrode 110 is appliedto first electrode 159 of semiconductor device 100, a breakdown voltagemay be reduced due to concentration of a high electric field insemiconductor device 100. To suppress the reduction in the breakdownvoltage, termination region 150 is provided, and in this example,termination region 150 is formed to have a curvature at corners ofsemiconductor device 100 as illustrated in FIG. 1B. For example,termination region 150 can be expressed by at least two straight regions150 a whose inner periphery and outer periphery are formed by a straightline, and sector region 150 b having a curved line. Sector region 150 bis formed to connect the ends of at least two straight regions 150 a. Inthis example, the inner periphery and the outer periphery of each of thestraight regions 150 a are formed only by a straight line, but a part ofthe inner perimeter and a part of the outer perimeter may not be linear.In addition, two regions which are connected to sector region 150 b arenot limited to be straight region 150 a, and may be a region having aninner perimeter and outer perimeter formed by a curved line with acurvature larger than the curvature of sector region 150 b, for example.For simplifying the description, surface 102S of drift layer 102 ofsemiconductor device 100 cut into a rectangular shape is divided intonine regions. In surrounding region 102E, a part including the sectorregion of termination region 150 is defined as region 102EC and a partincluding the straight region of termination region 150 is defined asregion 102EL. Thus, termination region 150 is divided into four cornerregions 102EC and four regions 102EL other than corner regions 102EC.

The corners of effective region 102A may have a curvature. In this case,as illustrated in FIG. 2, corner regions of effective region 102Aincluding portions in which the boundary between effective region 102Aand surrounding region 102E is formed by a curved line are defined as102AC, regions of effective region 102A including portions in which theboundary between effective region 102A and surrounding region 102E isformed by a straight line is defined as 102AL, and the remaining regionof effective region 102A is defined as 102AM. Thus, effective region102A is divided into four sector regions 102AC, four rectangular regions102AL, and remaining region 102AM. Returning again to FIG. 1B whichshows that the corners of effective region 102A do not have a curvature,effective region 102A and region 102AM coincide with each other. Inother words, effective region 102A is not divided.

In the examples illustrated in FIGS. 1B and 2, in termination region 150located in region 102EC, the inner circumference and outer circumferenceof the rings in FLR region 152 and the outer circumference of guard ringregion 151 have same center of curvature P. In the example in FIG. 2,the inner circumference of guard ring region 151 also has same center ofcurvature P. While the inner circumference and outer circumference ofall rings in FLR region 152 have center of curvature P in the examplesin FIGS. 1B and 2, the inner circumference and outer circumference of atleast one ring may have center of curvature P.

In the example in FIG. 2, center of curvature P is present withineffective region 102A. In other words, center of curvature P is insidethe inner circumference of guard ring region 151. When the distance frompoint P to the inner circumference of guard ring region 151 is definedas radius of curvature r₀, r₀ assumes a positive value in the example inFIG. 2, while it is zero in the example in FIG. 1B. In the presentapplication, attention is focused on this radius of curvature r₀.

In a conventional semiconductor device, radius of curvature r₀ issufficiently large, such as 100 μm or more. The reduction in thebreakdown voltage can be suppressed by sufficiently increasing theradius of curvature r₀, whereas the area of the effective region 102A isdecreased, which reduces an amount of electric current in an on state ofthe semiconductor device. In other words, on resistance or on voltage isincreased. The inventor of the present application has found that, evenif radius of curvature r₀ is sufficiently decreased, extreme reductionof the breakdown voltage does not occur. With the decrease in radius ofcurvature r₀, the inner circumference of guard ring region 151 becomesangular in regions 102AC illustrated in FIG. 2. Accordingly, the area ofeffective region 102A is increased, which increases an amount ofelectric current in the on state of the semiconductor device.

An avalanche breakdown voltage of semiconductor device 100 was evaluatedwith radius of curvature r₀ being used as a parameter. FIG. 3illustrates a result obtained by plotting avalanche breakdown voltageswhen radius of curvature r₀ is zero, 3 μm, 10 μm, 50 μm, and 130 μm. Thebreakdown voltage was standardized by the area of effective region 102A,and a voltage when the electric current value was 0.01 A/cm² was definedas the breakdown voltage. In a semiconductor device having radius ofcurvature r₀ being 100 μm or more which is typical in a conventionalsemiconductor device, a breakdown voltage of about 1990 V was obtained,and in a semiconductor device having radius of curvature r₀ being from10 μm to 50 μm inclusive, a breakdown voltage of an almost equal levelwas also obtained.

This indicates that the radius of curvature of the inner circumferenceof the guard ring region may be from 10 μm to 50 μm inclusive. With thisconfiguration, a sufficient area of effective region 102A can be ensuredwhile maintaining a high breakdown voltage equal to the breakdownvoltage of the conventional semiconductor device having a radius ofcurvature being 100 μm or more, whereby an effect of enabling use of thesemiconductor device in a large electric current environment can beobtained.

On the other hand, a reduction in the breakdown voltage was observed ina semiconductor device with radius of curvature r₀ being 10 μm or lessas illustrated in FIG. 3. However, it was confirmed that such reductionin the breakdown voltage was an insignificant level for practicalapplications. To provide the ground thereof, reverse current-voltagecharacteristics of semiconductor device 100 is illustrated in FIG. 4.Herein, the reverse direction indicates a case where a negative voltagewith respect to second electrode 110 is applied to first electrode 159.In FIG. 4, reverse current-voltage characteristics of semiconductordevices 100 with radius of curvature r₀ being zero, 10 μm, and 50 μm areillustrated all together. It is understood that a current extremelyincreases around a point where the voltage exceeds 1950 V, whichindicates that an avalanche current flows. The avalanche breakdownvoltage at that time is a little smaller in the semiconductor devicewith a radius of curvature r₀ of zero than in the semiconductor devicewith a radius of curvature r₀ of 50 μm. On the other hand, regarding aleakage current zone where the voltage is 1900 V or lower, it is foundthat the waveforms of the semiconductor devices with radius of curvaturer₀ being zero, 10 μm, and 50 μm overlap one another almost perfectly. Tosum it up, a decrease in radius of curvature r₀ has no effect on aleakage current and raises no problem for practical applications,although a slight reduction in the breakdown voltage is observed.

In other words, the radius of curvature of the inner circumference ofthe guard ring region may be 10 μm or less. With this configuration, asufficient area of effective region 102A can be ensured, and an effectin which the semiconductor device can be used in a large electriccurrent environment while suppressing an increase in a leakage currentcan be obtained, although a slight reduction in the breakdown voltage isobserved, compared with the conventional semiconductor device with aradius of curvature of 100 μm or more. Further, if the radius ofcurvature of the inner circumference of guard ring region 151 is zero asillustrated in the example in FIG. 1B, the area of effective region 102Acan be maximized while suppressing the reduction in the breakdownvoltage, which leads to an effect of enabling use of the semiconductordevice in a large electric current environment.

In the example in FIG. 1B, when the radius of curvature of the innercircumference of guard ring region 151 is zero, center of curvature P ison the four corners of effective region 102A, that is, on the corners ofthe inner circumference of guard ring region 151. The state where theradius of curvature of the inner circumference of guard ring region 151is zero can be restated as a state where radius of curvature P coincideswith the inner circumference of guard ring region 151. In the example inFIG. 1B, the inner circumference of guard ring region 151 hasright-angled corners but is not limited thereto.

In the conventional semiconductor device with a radius of curvature of100 μm or more, the size of the entire semiconductor device needs to beincreased to increase the area of the effective region. On the otherhand, in the semiconductor device according to the present exemplaryembodiment, an effective region having an area equal to the area of theeffective region of the conventional semiconductor device can beimplemented with a size smaller than the size of the conventionalsemiconductor device.

In the illustrated example, termination region 150 surrounding almostrectangular effective region 102A has the above-mentioned sectorsections outside the four corners of effective region 102A,respectively. It is to be noted that the termination region in thepresent exemplary embodiment may have the above-mentioned sector sectionoutside at least one of the corners of effective region 102A. Effectiveregion 102A is also not limited to have a rectangular planar shape.

(Method for Producing Semiconductor Device)

Next, how to produce semiconductor device 100 according to thisexemplary embodiment will now be described herein with reference toFIGS. 5 to 13. FIGS. 5 to 13 are each a sectional view illustrating apart of the method for producing semiconductor device 100 according tothe present exemplary embodiment.

First, semiconductor substrate 101 is prepared. Semiconductor substrate101 is, for example, a low resistance, n-type 4H—SiC (0001) off-cutsubstrate cut at an angle of 4 degrees in the direction of <11-20>, forexample, and having a resistivity of approximately 0.02 Ωcm.

As illustrated in FIG. 5, high resistance, n-type drift layer 102 isformed on semiconductor substrate 101 through epitaxial growth. Beforedrift layer 102 is formed, buffer layer 102B made of SiC that is n-type,and that has a higher impurity concentration may be deposited onsemiconductor substrate 101. An impurity concentration of the bufferlayer is 1×10¹⁸ cm⁻³, for example, and a thickness of the buffer layeris 1 μm, for example. Drift layer 102 is made of n-type 4H—SiC, forexample, and an impurity concentration and thickness of drift layer 102are 6×10¹⁵ cm⁻³ and 11 μm, respectively. The concentration and thicknessare determined, as appropriate, for obtaining a required breakdownvoltage, and therefore, not limited to the values described above.

Next, as illustrated in FIG. 6, mask 1600 made of SiO₂, for example, isformed on drift layer 102, and then, Al ions are implanted into driftlayer 102, for example. Thus, ion implantation regions 1510 and 1520 areformed in drift layer 102. Ion implantation regions 1510 and 1520 laterserve as guard ring region 151 and FLR region 152, respectively. If theshape of mask 1600 in a central region is rectangular or square, theinner circumference of guard ring region 151 has right-angled corners.However, in a practical sense, the corners of mask 1600 in the centralregion are not perfectly right-angled but may have a radius of curvatureof several μm.

Although not illustrated, impurities of a first conductivity type may beimplanted to the back surface of semiconductor substrate 101, asnecessary, to further increase the concentration of the firstconductivity type impurities at the back surface.

Next, as illustrated in FIG. 7, after mask 1600 is removed, a heattreatment is performed at a temperature in a range from 1500° C. to1900° C. inclusive, whereby guard ring region 151 and FLR region 152 arerespectively formed from ion implantation regions 1510 and 1520. Beforethe heat treatment is performed, a carbon film may be deposited on asurface of drift layer 102, and then, after the heat treatment isperformed, the carbon film may be removed. After this process, a thermaloxide film may be formed on the surface of drift layer 102, and then,the thermal oxide film may be removed through etching to clean thesurface of drift layer 102. Width W of guard ring region 151 illustratedin FIG. 1A is 15 μm, for example. FLR region 152 includes a plurality ofrings to surround guard ring region 151. The width of the implantationregion of each of the plurality of FLRs is from 1 μm to 2 μm, forexample, and the space between FLRs is about 0.7 μm to 5 μm. The widthof each FLR and the space between FLRs may be fixed or vary forobtaining a required breakdown voltage of semiconductor device 100. Inthe present exemplary embodiment, FLR region 152 has ten FLRs. However,the number of FLRs may be changed for obtaining a required breakdownvoltage. For example, FLR region 152 may have about twenty-five FLRs.The maximum concentration of the second conductivity type impurities intermination region 150 including guard ring region 151 and FLR region152 is about 2×10²⁰ cm⁻³, for example, and the depth is 1 μm, forexample. The depth is defined at a location where the concentration ofthe second conductivity type impurities in the termination region 150becomes equal to the concentration of first conductivity type impuritiesin drift layer 102.

Next, as illustrated in FIG. 8, insulating film 111 made of SiO₂, forexample, is formed on the surface of drift layer 102 with a thickness of500 nm, for example, to protect the surface. Then, Ni, for example, isdeposited on the back surface of semiconductor substrate 101 with athickness of about 200 nm and then heat treated at about 1000° C. toform second electrode 110. Second electrode 110 forms an ohmic contactwith the back surface of semiconductor substrate 101. The material ofthe electrode is not limited to Ni, and any metals that can form asilicide may be used, such as Ti or Mo.

Next, a mask is formed through photo-resist to allow a part of guardring region 151 and drift layer 102 inside guard ring region 151 toexpose through wet etching, for example. The mask is then removed. Inthis way, insulating film 111 having an opening can be obtained asillustrated in FIG. 9.

Next, as illustrated in FIG. 10, a first electrode conductive film(first electrode 159) is deposited so as to wholly cover insulating film111 having the opening and drift layer 102 exposed in the opening. Thefirst electrode conductive film is made of a material such as Ti, Ni,and Mo. A thickness of the first electrode conductive film is 200 nm,for example. Thereafter, a heat treatment is performed for semiconductorsubstrate 101 including first electrode conductive film (first electrode159) at a temperature in a range from 100° C. to 700° C. inclusive. Thefirst electrode conductive film (first electrode 159) thus forms aSchottky contact with drift layer 102.

Next, a front face electrode conductive film is deposited on the firstelectrode conductive film (first electrode 159). The front faceelectrode conductive film is a metal film that contains Al, for example,and that has a thickness of approximately 4 μm. A mask is formed on thefront face electrode conductive film, and unnecessary portions areetched to remove a part of the first electrode conductive film (firstelectrode 159) together. Thus, a part of insulating film 111 is exposed.By removing the mask after the part of the front face electrodeconductive film is etched, front face electrode 112 and patterned firstelectrode 159 are formed as illustrated in FIG. 11. The etching duringthis process may be wet etching or dry etching.

Next, passivation film 114 is formed, as necessary, as illustrated inFIG. 12. First, an insulating film (passivation film 114) which is anorganic film made of SiN or polyimide and which is to be used as apassivation film is formed on insulating film 111 and front faceelectrode 112, which are exposed. Thereafter, a mask is prepared whichhas an opening for exposing the insulating film (passivation film 114)formed on front face electrode 112 as a passivation film and an end ofsemiconductor device 100, and a part of the passivation film is etchedby dry etching, wet etching, development, or other processes to expose apart of front face electrode 112 and the end of semiconductor device100. The mask is then removed. Thus, passivation film 114 having anopening through which a part of front face electrode 112 is exposed isobtained as illustrated in FIG. 12. Passivation film 114 may be aninsulating body. For example, passivation film 114 may be an SiO₂ filmor an organic film made of polybenzoxazole, for example.

Next, as illustrated in FIG. 13, back face electrode 113 is formed asrequired. A process of forming back face electrode 113 may be performedbefore a process of forming passivation film 114 described above, orbefore a process of forming front face electrode 112. For back faceelectrode 113, Ti, Ni, and Ag are deposited in order from a sideabutting second electrode 110, for example. Respective thicknesses ofTi, Ni, and Ag are 0.1 μm, 0.3 μm, and 0.7 μm, for example.Semiconductor device 100 is formed through the above-describedprocesses.

(Modifications)

Modifications of the semiconductor device according to the presentexemplary embodiment will now be described.

FIGS. 14A to 16B illustrate a semiconductor device having a junctionbarrier Schottky (JBS) structure by forming barrier region 153 ineffective region 102A with respect to termination region 150 which isthe gist of the present disclosure. A plurality of barrier regions 153of a second conductivity type may be formed in a region, which is insidetermination region 150, in drift layer 102 as viewed in the normaldirection of semiconductor substrate 101. The formation of barrierregions 153 can reduce a Schottky leakage current when a reverse biaswith respect to the Schottky contact formed between first electrode 159and drift layer 102 is applied. Barrier regions 153 may be formedsimultaneously with termination region 150.

Semiconductor device 200 illustrated in FIGS. 14A and 14B has aplurality of barrier regions 153 equally spaced from each other andextending in one direction. The width of each barrier region 153 is from1 μm to 2 μm, for example, and the space between adjacent barrierregions 153 is from 2 μm to 10 μm, for example. The width of barrierregion 153 may be smaller than the space between adjacent barrierregions 153.

Semiconductor device 300 illustrated in FIGS. 15A and 15B has aplurality of rectangular barrier regions 153 equally spaced from eachother. The length of one side of each barrier region 153 is from 1 μm to2 μm, for example, and the space between adjacent barrier regions 153 isfrom 2 μm to 10 nm, for example. The width of barrier region 153 may besmaller than the space between adjacent barrier regions 153. Barrierregion 153 in FIGS. 15A and 15B has a square shape but may have otherpolygonal shapes including a rectangular shape or a circular shape.

Semiconductor device 400 illustrated in FIGS. 16A and 16B has barrierregions 153 illustrated in FIG. 15B, barrier regions 153 being displacedrelative to one another by ½ pitch by slightly changing the positions ofbarrier regions 153. As illustrated in FIG. 16B, a part of the innercircumference of guard ring region 151 in region 102EL may overlapbarrier regions 153. Although not illustrated, barrier regions 153 mayoverlap the inner circumference of guard ring region 151 in region102EC. In a configuration in which the inner circumference of guard ringregion 151 partially overlap barrier region 153, the inner circumferenceof guard ring region 151 overlapping barrier region 153 can be specifiedby the outer circumference of guard ring region 151 and width W of guardring region 151. The same is applied to a configuration in which theinner circumference of guard ring region 151 abuts barrier regions 153.

The shape and arrangement of barrier regions 153 described above are notlimited to those described above.

Other modifications of the semiconductor device according to theexemplary embodiment will further be described below.

FIGS. 17A and 17B illustrate semiconductor device 500A formed by addingseal ring 1120 to semiconductor device 100 illustrated in FIG. 1A in aregion outside termination region 150 and inside the end ofsemiconductor device 100. Barrier metal 1590 may be provided below sealring 1120. When seal ring 1120 is provided, a part of drift layer 102 isexposed to be in contact with barrier metal 1590 by forming an openingin a part of insulating film 111. In addition, termination implantationregion 154 of a second conductivity type may be provided in the regionabutting barrier metal 1590. In this case, barrier metal 1590 may bedirectly in contact with termination implantation region 154. Insemiconductor device 500A illustrated in FIGS. 17A and 17B, terminationimplantation region 154 is disposed to be in contact with the end of thesemiconductor device while being separated from the outer circumferenceof FLR region 152. However, termination implantation region 154 may havea ring shape with a constant width as illustrated in FIGS. 17C and 17D.The current-voltage characteristics of semiconductor device 500A arealmost the same, whether termination implantation region 154 is disposedto be in contact with the end of the semiconductor device or not to bein contact therewith. In addition, the center of curvature of the innercircumference of termination implantation region 154 at the corners ofthe semiconductor device may coincide with point P.

Semiconductor device 500B illustrated in FIG. 18 has a structure formedby eliminating termination implantation region 154 from semiconductordevice 500A. In this case, barrier metal 1590 may be directly in contactwith drift layer 102. Even if termination implantation region 154 is notprovided, the current-voltage characteristics of semiconductor device500B is almost the same as the current-voltage characteristics ofsemiconductor device 500A illustrated in FIGS. 17A to 17D.

Semiconductor device 500C illustrated in FIG. 19 has a structure formedby eliminating barrier metal 1590 from semiconductor device 500A. Inthis case, seal ring 1120 may be directly in contact with terminationimplantation region 154.

Semiconductor device 500D illustrated in FIG. 20 has a structure formedby eliminating barrier metal 1590 and termination implantation region154 from semiconductor device 500A. In this case, seal ring 1120 may bedirectly in contact with drift layer 102.

Barrier metal 1590 may be formed simultaneously with first electrode159. In addition, seal ring 1120 may be formed simultaneously with frontface electrode 112. Further, termination implantation region 154 may beformed simultaneously with termination region 150. In FIGS. 17A, 17B,and 19, termination implantation region 154 is disposed to be in contactwith the end of semiconductor device. However, termination implantationregion 154 may be disposed to be separated from the end of thesemiconductor device as illustrated in FIGS. 17C and 17D. In addition,termination implantation region 154 may be separately formed from amaterial of a first conductivity type.

Seal ring 1120 illustrated in FIGS. 17A to 20 may be covered bypassivation film 114.

In addition, as compared to semiconductor device 100 illustrated in FIG.1B in which the inner circumference of guard ring region 151 is definedwith the radius of curvature at point P being zero, the area of theinner circumference portion of the guard ring region at the corners maybe increased by setting point Q inside point P as another center ofcurvature as illustrated in FIG. 21. Point P is positioned in guard ringregion 151, and point Q is positioned inside the inner circumference ofguard ring region 151. Based on width W (μm) of guard ring region 151,the outer circumference of guard ring region 151 may be 50+W (μm). Thiscondition for the outer circumference is the same as the condition ofthe examples illustrated in FIGS. 1B and 2. However, in this case,effective region 102A is narrowed. When the radius of curvature withpoint Q being the center of curvature is defined as r_(i), the distancebetween points P and Q is represented as follows, compared to theexample in FIG. 1B where effective region 102A is rectangle and thecenter of curvature P coincides with the corners of effective region102A.

PQ=√{square root over (2)}×r _(i)  [Equation 1]

As in the examples illustrated in FIGS. 1B and 2, r_(i) may be 10 μm orless. The semiconductor device illustrated in FIG. 21 provides effectssimilar to the effects provided by the semiconductor devices in FIGS. 1Band 2.

The configurations of the semiconductor devices according to the presentdisclosure and materials of the components are not limited to theconfigurations and the materials of the above-described examples. Forexample, the material of first electrode 159 is not limited to Ti, Ni,and Mo described above. A material selected from a group consisting ofother metals forming a Schottky contact with drift layer 102 and alloysand compounds thereof may be used for first electrode 159.

In addition, a barrier film containing TiN, for example, may be formedon first electrode 159 and under front face electrode 112. A thicknessof the barrier film is 50 nm, for example.

The above exemplary embodiments in the present disclosure have describeda case where silicon carbide is 4H—SiC. However, silicon carbide may beanother polytype, such as 6H—SiC, 3C—SiC, and 15R—SiC. The exemplaryembodiments of the present disclosure have described a case where themain surface of the SiC substrate is the face that is off-cut from a(0001) surface (Si face). However, the main surface of the SiC substratemay be a (11-20) surface, a (1-100) surface, a (000-1) surface (C face),or an off-cut surface of one of them. An Si substrate may be used assemiconductor substrate 101. A 3C—SiC drift layer may be formed on theSi substrate. In this case, annealing for activating impurity ionsimplanted into 3C—SiC may be performed at a temperature equal to orlower than a melting point of the Si substrate.

The present disclosure can be used for power semiconductor devices to bemounted on consumer power converters, on-board power converters, andpower converters for industry machines, for example.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conductivity type having a mainsurface and a back surface; a silicon carbide semiconductor layer of afirst conductivity type disposed on the main surface of thesemiconductor substrate; a termination region of a second conductivitytype disposed in the silicon carbide semiconductor layer; a firstelectrode which is disposed on the silicon carbide semiconductor layerand forms a Schottky contact with the silicon carbide semiconductorlayer; and a second electrode which is disposed on the back surface ofthe semiconductor substrate and forms an ohmic contact with thesemiconductor substrate, wherein the termination region is disposed tosurround a part of a surface of the silicon carbide semiconductor layeras viewed in a normal direction of the main surface of the semiconductorsubstrate, the termination region includes a guard ring region of asecond conductivity type abutting the surface of the silicon carbidesemiconductor layer and a field limiting ring (FLR) region disposed tosurround the guard ring region while being separated from the guard ringregion, the FLR region including a plurality of rings of a secondconductivity type, the first electrode has a face abutting the siliconcarbide semiconductor layer, the first electrode abuts the guard ringregion at an edge of the face abutting the silicon carbide semiconductorlayer, the termination region includes a sector section as viewed in anormal direction of the surface of the silicon carbide semiconductorlayer, and in the sector section, an inner circumference and an outercircumference of at least one of the plurality of rings and an innercircumference and an outer circumference of the guard ring region have asame first center of curvature, the first center of curvature beingpositioned inside the inner circumference of the guard ring region, anda radius of curvature of the inner circumference of the guard ringregion is 50 μm or less.
 2. The semiconductor device according to claim1, wherein the radius of curvature of the inner circumference of theguard ring region is 10 μm or more.
 3. The semiconductor deviceaccording to claim 1, wherein the radius of curvature of the innercircumference of the guard ring region is 10 μm or less.
 4. Thesemiconductor device according to claim 1, wherein the innercircumference of the guard ring region has a right-angled corner.
 5. Thesemiconductor device according to claim 1, wherein the terminationregion further includes at least two straight parts whose innerperimeter and outer perimeter are formed by a straight line, and thesector section is disposed to connect ends of the at least two straightparts.
 6. A semiconductor device comprising: a semiconductor substrateof a first conductivity type having a main surface and a back surface; asilicon carbide semiconductor layer of a first conductivity typedisposed on the main surface of the semiconductor substrate; atermination region of a second conductivity type disposed in the siliconcarbide semiconductor layer; a first electrode which is disposed on thesilicon carbide semiconductor layer and forms a Schottky contact withthe silicon carbide semiconductor layer; and a second electrode which isdisposed on the back surface of the semiconductor substrate and forms anohmic contact with the semiconductor substrate, wherein the terminationregion is disposed to surround a part of a surface of the siliconcarbide semiconductor layer as viewed in a normal direction of the mainsurface of the semiconductor substrate, the termination region includesa guard ring region of a second conductivity type abutting the surfaceof the silicon carbide semiconductor layer and a field limiting ring(FLR) region disposed to surround the guard ring region while beingseparated from the guard ring region, the FLR region including aplurality of rings of a second conductivity type, the first electrodehas a face abutting the silicon carbide semiconductor layer, the firstelectrode abuts the guard ring region at an edge of the face abuttingthe silicon carbide semiconductor layer, the termination region includesa sector section as viewed in a normal direction of the surface of thesilicon carbide semiconductor layer, and in the sector section, an innercircumference and an outer circumference of at least one of theplurality of rings and an outer circumference of the guard ring regionhave a same first center of curvature, the first center of curvaturebeing positioned on the inner circumference of the guard ring region orwithin the guard ring region.
 7. The semiconductor device according toclaim 6, wherein, when a width of the guard ring region is defined as Wμm, a radius of curvature of the outer circumference of the guard ringregion is 50+W μm or less.
 8. The semiconductor device according toclaim 6, wherein the inner circumference of the guard ring region has asecond center of curvature different from the first center of curvature,the second center of curvature is positioned inside the innercircumference of the guard ring region as viewed in a normal directionof the surface of the silicon carbide semiconductor layer, and a radiusof curvature of the inner circumference of the guard ring region is 10μm or less.
 9. The semiconductor device according to claim 6, whereinthe termination region further includes at least two straight partswhose inner perimeter and outer perimeter are formed by a straight line,and the sector section is disposed to connect ends of the at least twostraight parts.